This invention relates to output circuits, input circuits and input/output circuits which can be built-in in an integrated circuit or an IC. More specifically, this invention relates to a plurality of improvements developed for providing three independent groups of circuits which are allowed to be built-in in an IC.
The circuits belonging to the first group of this invention are output circuits each of which acts as an interface employable for outputting a voltage signal to an external circuit which works under a power supply of which the voltage is e.g. 5V which is higher than the voltage e.g. 3V which is the voltage of a power supply under which the output circuit works. The ultimate purpose of this invention is to provide output circuits which are possible to output such voltage signals quickly with a higher speed without consuming a large amount of electric power. More precisely, the output circuits belong to the first group of this invention are output circuits which are possible to increase the potential level of such an output signal at least to the level of the voltage e.g. 3V which is the voltage of a power supply employed in the output circuits, very quickly, without consuming a large amount of electric power.
The circuits belonging to the second group of this invention are input circuits each of which acts as an interface employable for receiving a voltage signal from an external circuit which works under a power supply of which the voltage is e.g. 5V which is higher than the voltage e.g. 3V which is the voltage of a power supply under which the input circuit works. The ultimate purpose of this invention is to provide input circuits which are possible to receive voltage signals of which the potential is higher than the voltage of a power supply employed in the input circuit and forward the voltage signals toward the next stage circuit in a voltage corresponding to the full amount of the voltage of a power supply employed in the input circuit. More precisely, the input circuits belonging to the second group of this invention are input circuits which are possible to forward a voltage signal having a sufficient potential level, with respect to the VIH rule, to the next stage circuit. More specifically, the input circuits belonging to the second group of this invention are input circuits which receive a voltage signal from a circuit which works under a power supply of which the voltage is higher than the voltage of a power supply under which the input circuits work and forward the voltage signal having a voltage of the full amount of the voltage of a power supply under which the input circuits work or VDD, rather than (VDD-Vth) to the next stage circuit.
The circuits belonging to the third group of this invention are input/output circuits each of which is convertible between an output circuit having an advantage referred to above and an input circuit having an advantage referred to above.
An output circuit allowable to be built-in in an integrated circuit and which is available in the prior art and an input circuit allowable to be built-in in an integrated circuit and which is available in the prior art will be described below, referring to drawings.
Referring to FIGS. 1 and 2, an output circuit allowable to be built-in in an integrated circuit and which is available in the prior art has an open drain circuit consisting of an n channel normally on type field effect transistor (N101) connected a pull-up resister (R1) through a xe2x80x9cPADxe2x80x9d of the IC in which the output circuit is built-in. The pull-up resister (R1) is arranged outside the IC and works under a power supply Vcc of e.g. 5V, despite the output circuit works under a power supply of e.g. 3V. The n channel normally on type field effect transistor (N101) has a function to reduce the voltage applied between the source and the drain of the n channel normally on type field effect transistor (N102). FIG. 2 shows that the voltage of the output signal very slowly increases up to the voltage of Vcc or 4V in this example, in excess of the voltage level of the voltage signal which is outputted from this output circuit and which is shown by (IN). It is noted that a very long time is required for transmission of a voltage signal having a potential level of e.g. 3V to an external circuit which works under a power supply of a higher voltage of e.g. 5V. Incidentally, it is noted the output circuit can be employed as the output circuit of an IC having a less amount of dielectric strength.
Referring to FIGS. 3 and 4, an input circuit allowable to be built-in in an integrated circuit and which is available in the prior art has an n channel normally on type field effect transistor (N100) which has a function to reduce the voltage of an input signal which is inputted through a xe2x80x9cPADxe2x80x9d of the IC and which has a voltage range of zero through 5V to a voltage range ranging from zero to the voltage difference between the VDD voltage or the power supply voltage of circuit and the threshold voltage of the n channel normally on type field effect transistor (N100), before forwarding the input signal to the next stage circuit produced the IC. Therefore, the input circuit can be employed for an integrated circuit having a less amount of dielectric strength. The threshold voltage of the IC is designed to be less than that of the ordinary input circuit. In the drawing, xe2x80x9cPADxe2x80x9d means the bonding pad for the input circuit. FIG. 4 shows the voltage of an input signal received at an input terminal (IN) is reduced to the potential level of the node (Y), before being applied to an amplifier and forwarded to the next stage circuit.
In the first place, referring to FIG. 2, the output signal outputted from the output circuit illustrated in FIG. 1 increases at a rate determined by a time constant which is further determined by the amount of the pull-up resister (R1). This means that if a high operation speed is required, a less amount of the pull-up resister (R1) is required. If the amount of the pull-up resister (R1) is made less, the power consumption increases accordingly, vice versa.
This is a drawback inevitably involved with the foregoing output circuit available in the prior art, described referring to FIGS. 1 and 2.
In the second place, supposing the power supply voltage of the input circuit illustrated in FIG. 3 or the VDD is 3V, an input signal of 5V inputted into the input circuit through the xe2x80x9cPADxe2x80x9d is reduced to a value which is VDD less the threshold voltage of the n channel normally on type field effect transistor (N100), (VDD-Vth) or approximately 2.3V, before being applied to the node (Y). Accordingly, it is not easy for such an input circuit to satisfy the requirement of VIH, which is a regulation inspecting whether or not an xe2x80x9cHxe2x80x9d level voltage issued by an input circuit has a sufficient amount of margin with respect to the threshold value of the internal circuit of the input circuit.
This is a drawback inevitably involved with the foregoing input circuit available in the prior art, described referring to FIGS. 3 and 4.
Accordingly, an object of this invention is to provide output circuits which are allowed to be built-in in an integrated circuit and which can output voltage signals into an external circuit which works under a power supply of which the voltage is higher than the voltage of a power supply under which the output circuits work, with a higher operation rate and without consuming a large amount of electric power.
Another object of this invention is to provide input circuits which are allowed to be built-in in an integrated circuit and which can receive input voltage signals from an external circuit which works under a power supply of which the voltage is higher than the voltage of a power supply under which the input circuits work, and to forward the input signals to the next stage circuit, in the voltage corresponding to the full amount of the voltage of a power supply under which the input circuits work, or voltage signals sufficiently high with respect to the VIH rule (voltage signals having a voltage high enough to remain a sufficient amount of margin stipulated in the VIH rule.).
A further object of this invention is to provide input/output circuits which are allowed to be built-in in an integrated circuit and which are convertible between output circuits which can output voltage signals into an external circuit which works under a power supply of which the voltage is higher than the voltage of a power supply under which the output circuits work, with a higher operation rate and without consuming a large amount of electric power and input circuits which can receive input voltage signals from an external circuit which works under a power supply of which the voltage is higher than the voltage of a power supply under which the input circuits work, and to forward the inputted signals to the next stage circuit, in the voltage corresponding to the full amount of the voltage of a power supply under which the input circuits work, or voltage signals sufficiently high with respect to the VIH rule (voltage signals having a voltage high enough to remain a sufficient amount of margin stipulated in the VIH rule.).
An output circuit (This corresponds to claim 1.) in accordance with the first embodiment of this invention described referring to FIG. 5 is defined as:
an output circuit comprising:
a first normally off type field effect transistor ((P1) of FIG. 5) having a channel of one conductivity, having a gate connected a first node, having a first electrode connected a first power supply and having a second electrode connected a second node,
a second normally off type field effect transistor ((P2) of FIG. 5) having a channel of one conductivity, having a gate connected a third node, having a first electrode connected the second node, having a second electrode connected a fourth node and having a substrate connected a fifth node which is floating,
a third normally off type field effect transistor ((P4) of FIG. 5) having a channel of one conductivity, having a gate connected a sixth node, having a first electrode connected the third node, having a second electrode connected the fourth node and having a substrate connected the fifth node,
a fourth normally off type field effect transistor ((N3) of FIG. 5) having a channel of the opposite conductivity, having a gate connected the sixth node, having a first electrode connected the third node and having a second electrode connected a second power supply, and an inverter means having an input terminal connected the fourth node and an output terminal connected the sixth node.
Three modifications stem from the foregoing output circuit defined in claim 1.
The first modification (This corresponds to claim 3.) is the output circuit defined in claim 1 to which a fifth normally off type field effect transistor ((P3) of FIG. 3) having a channel of one conductivity having a gate connected the third node, having a first electrode connected the second node, having a second electrode connected the fifth node, and having a substrate connected the fifth node, is newly introduced.
The second modification (This corresponds to claim 4.) is the output circuit defined in claim 1 to which a sixth normally off type field effect transistor ((P5) of FIG. 3) having a channel of one conductivity having a gate connected the first power supply, having a first electrode connected the second node, having a second electrode connected the firth node and having a substrate connected the fifth node, is newly introduced.
The third modification (This corresponds to claim 5.) is the output circuit defined in claim 1 to which:
a first input terminal connected the first node,
a second input terminal connected a seventh node,
an output terminal connected the fourth node, and
a seventh normally off type field effect transistor ((N1) of FIG. 3) having a channel of the opposite conductivity having a gate connected the seventh node, having a first electrode connected said second power supply and having a second electrode connected the fourth node, are newly introduced.
An input circuit (This corresponds to claim 2.) in accordance with the second embodiment of this invention described referring to FIG. 7, is the output circuit defined in claim 1 to which a delay circuit connected between the gate of the third normally off type field effect transistor ((P4) of FIG. 5) having a channel of one conductivity and the gate of the fourth normally off type field effect transistor ((N3) of FIG. 3) having a channel of the opposite conductivity, is newly introduced.
An output circuit (This corresponds to claim 6.) in accordance with the third embodiment of this invention described referring to FIG. 9 is defined as:
an output circuit comprising:
a first normally off type field effect transistor ((P1) of FIG. 9) having a channel of one conductivity, having a gate connected a first node, having a first electrode connected a first power supply and having a second electrode connected a second node,
a second normally off type field effect transistor ((P2) of FIG. 9) having a channel of one conductivity, having a gate connected a third node, having a first electrode connected the second node, having a second electrode connected a fourth node and having a substrate connected a fifth node which is floating,
a third normally off type field effect transistor ((P4) of FIG. 9) having a channel of one conductivity, having a gate connected a sixth node, having a first electrode connected the third node, having a second electrode connected the fourth node and having a substrate connected the fifth node,
a fourth normally off type field effect transistor ((N7) of FIG. 9) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected fourth node and having a second electrode connected a seventh node,
a fifth normally off type field effect transistor ((P7) of FIG. 9) having a channel of one conductivity, having a gate connected the third node, having a first electrode connected the seventh node, having a second electrode connected the fourth node and a substrate connected the fifth node,
an inverter means having an input terminal connected the seventh node and an output terminal connected an eighth node,
a sixth normally off type field effect transistor ((N3) of FIG. 9) having a channel of the opposite conductivity, having a gate connected the eighth node, having a first electrode connected a second power supply and having a second electrode connected the sixth node, and
a seventh normally off type field effect transistor ((N7) of FIG. 9) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the sixth node and having a second electrode connected the third node.
Four modifications stem from the foregoing output circuit defined in claim 6.
The first modification (This corresponds to claim 7.) is the output circuit defined in claim 6 to which an eighth normally off type field effect transistor ((P6) of FIG. 9) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the first power supply, having a first electrode connected the first power supply and having a second electrode connected said seventh node, is newly introduced.
The second modification (This corresponds to claim 8.) is the output circuit defined in claim 6 to which a ninth normally off type field effect transistor ((P3) of FIG. 9) having a channel of one conductivity, having a gate connected the third node, having a first electrode connected the second node, having a second electrode connected the fifth node and having a substrate connected the fifth node, is newly introduced.
The third modification (This corresponds to claim 9.) is the output circuit defined in claim 6 to which a tenth normally off type field effect transistor ((P5) of FIG. 9) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the fourth node, having a second electrode connected the fifth node and having a substrate connected the fifth node, is newly introduced.
The fourth modification (This corresponds to claim 10.) is the output circuit defined in claim 6 to which:
a first input terminal connected the first node,
a second input terminal connected a ninth node,
an output terminal connected the fourth node,
an eleventh normally off type field effect transistor ((N1) of FIG. 9) having a channel of the opposite conductivity, having a gate connected the ninth node, having a first electrode connected the second power supply and having a second electrode connected a tenth node, and
a twelfth normally off type field effect transistor ((N2) of FIG. 9) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the tenth node and having a second electrode connected the fourth node are newly introduced.
An output circuit (This corresponds to claim 11.) in accordance with the fourth embodiment of this invention described referring to FIG. 11 is defined as:
an output circuit comprising:
a first normally off type field effect transistor ((P1) of FIG. 11) having a channel of one conductivity, having a gate connected a first node, having a first electrode connected a first power supply and having a second electrode connected a second node,
a second normally off type field effect transistor ((P2) of FIG. 11) having a channel of one conductivity, having a gate connected a third node, having a first electrode connected the second node, having a second electrode connected a fourth node and having a substrate connected a fifth node which is floating,
a third normally off type field effect transistor ((P4) of FIG. 11) having a channel of one conductivity, having a gate connected a sixth node, having a first electrode connected the third node, having a second electrode connected the fourth node and having a substrate connected the fifth node,
a fourth normally off type field effect transistor ((N7) of FIG. 11) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the fourth node and having a second electrode connected a seventh node,
a fifth normally off type field effect transistor ((P7) of FIG. 11) having a channel of one conductivity, having a gate connected the third node, having a first electrode connected the seventh node, having a second electrode connected the fourth node and having a substrate connected the fifth node,
a NOR gate means having a first input terminal connected the seventh node, having a second input terminal connected an eighth node and an output terminal connected a ninth node,
a sixth normally off type field effect transistor ((N3) of FIG. 11) having a channel of the opposite conductivity, having a gate connected the ninth node, having a first electrode connected a second power supply and having a second electrode connected a tenth node,
a seventh normally off type field effect transistor ((N4) of FIG. 11) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the tenth node and having a second electrode connected the third node,
an eighth normally off type field effect transistor ((N6) of FIG. 11) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the third node and having a second electrode connected an eleventh node,
a ninth normally off type field effect transistor ((N5) of FIG. 11) having a channel of the opposite conductivity, having a gate connected the eighth node, having a first electrode connected the eleventh node and having a second electrode connected the first node,
a tenth normally off type field effect transistor ((N8) of FIG. 11) having a channel of the opposite conductivity, having a gate connected a twelfth node, having a first electrode connected the tenth node and having a second electrode connected the sixth node, and
an eleventh normally off type field effect transistor ((P8) of FIG. 11) having a channel of one conductivity, having a gate connected the twelfth node, having a first electrode connected the first power supply and having a second electrode connected the sixth node.
Four modifications stem from the foregoing output circuit defined in claim 11.
The first modification (This corresponds to claim 12.) is the output circuit defined in claim 11 to which a twelfth normally off type field effect transistor ((P3) of FIG. 11) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the first power supply and having a second electrode connected the seventh node, is newly introduced.
The second modification (This corresponds to claim 13.) is the output circuit defined in claim 11 to which a thirteenth normally off type field effect transistor ((P3) of FIG. 11) having a channel of one conductivity, having a gate connected the third node, having a first electrode connected the second node, having a second electrode connected the fifth node and having a substrate connected the fifth node
is newly introduced.
The third modification (This corresponds to claim 14.) is the output circuit defined in claim 11 to which a fourteenth normally off type field effect transistor ((P5) of FIG. 11) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the fourth node, having a second electrode connected the fifth node and having a substrate connected the fifth node
is newly introduced.
The fourth modification (This corresponds to claim 15.) is the output circuit defined in claim 11 to which:
a first input terminal connected the first node,
a second input terminal connected a thirteenth node,
a third input terminal connected the twelfth node,
a fourth input terminal connected the eighth node,
an output terminal connected said fourth node,
a fifteenth normally off type field effect transistor ((N1) of FIG. 11) having a channel of the opposite conductivity, having a gate connected the thirteenth node, having a first electrode connected the second power supply and having a second electrode connected a fourteenth node, and
a sixteenth normally off type field effect transistor ((N2) of FIG. 11) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the fourteenth node and having a second electrode connected the fourth node
are newly introduced.
An input circuit (This corresponds to claim 16.) in accordance with the fifth embodiment of this invention described referring to FIG. 14 is defined as:
an input circuit comprising:
a first normally off type field effect transistor ((P1) of FIG. 14) having a channel of one conductivity, having a gate connected a first power supply, having a first electrode connected the first power supply and having a second electrode connected a first node,
a second normally off type field effect transistor ((P2) of FIG. 14) having a channel of one conductivity, having a gate connected a second node, having a first electrode connected the first node, having a second electrode connected a third node and having a substrate connected a fourth node which is floating,
a third normally off type field effect transistor ((P4) of FIG. 14) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the second node, having a second electrode connected the third node and having a substrate connected the fourth node,
a fourth normally off type field effect transistor ((N7) of FIG. 14) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the third node and having a second electrode connected a fifth node,
a fifth normally off type field effect transistor ((P7) of FIG. 14) having a channel of one conductivity, having a gate connected the second node, having a first electrode connected the fifth node, having a second electrode connected the third node and having a substrate connected the fourth node,
an inverter means having an input terminal connected the fifth node and an output terminal connected a sixth node,
a sixth normally off type field effect transistor ((N3) of FIG. 14) having a channel of the opposite conductivity, having a gate connected the sixth node, having a first electrode connected a second power supply and having a second electrode connected a seventh node, and
a seventh normally off type field effect transistor ((N4) of FIG. 14) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the seventh node and having a second electrode connected the second node.
A modification (This corresponds to claim 17.) stems from the foregoing input circuit defined in claim 16. The input circuit is the input circuit defined in claim 16 to which an eighth normally off type field effect transistor ((P6) of FIG. 14) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the first power supply and having a second electrode connected the fifth node, is newly introduced.
An input circuit (This corresponds to claim 18.) in accordance with the sixth embodiment of this invention described referring to FIG. 15 is the input circuit defined in claim 16 to which a ninth normally off type field effect transistor ((P21) of FIG. 15) having a channel of one conductivity, having a gate connected said second power supply, having a first electrode connected said first power supply and having a second electrode connected said fifth node, is newly introduced.
An input circuit (This corresponds to claim 19.) in accordance with the seventh embodiment of this invention described referring to FIG. 16 is the input circuit defined in claim 16 to which a tenth normally off type field effect transistor ((N21) of FIG. 16) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the fifth node and having a second electrode connected the second power supply, is newly introduced.
An input circuit (This corresponds to claim 20.) in accordance with the eighth embodiment of this invention described referring to FIG. 17 is the input circuit defined in claim 16 to which:
an eleventh normally off type field effect transistor ((N22) of FIG. 17) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the third node and having a second electrode connected an eighth node, and
a twelfth normally off type field effect transistor ((P22) of FIG. 17) having a channel of one conductivity, having a gate connected the eighth node, having a first electrode connected the first power supply, having a second electrode connected the third node and having a substrate connected the fourth node are newly introduced.
An input circuit (This corresponds to claim 21.) in accordance with the ninth embodiment of this invention described referring to FIG. 19 is the input circuit defined in claim 16 to which:
a thirteenth normally off type field effect transistor ((N23) of FIG. 19) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the second power supply and having a second electrode connected the eighth node, and
a fourteenth normally off type field effect transistor ((N24) of FIG. 19) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the eighth node and having a second electrode connected the third node
are newly introduced.
Three modifications stem from the input circuit defined in claim 16.
The first modification (This corresponds to claim 22.) is the input circuit defined in claim 16 to which a fifteenth normally off type field effect transistor ((P3) of FIG. 14) having a channel of one conductivity, having a gate connected the second power supply, having a first electrode connected the first node, having a second electrode connected the fourth node and having a substrate connected said fourth node, is newly introduced.
The second modification (This corresponds to claim 23.) is the input circuit defined in claim 16 to which a sixteenth normally off type field effect transistor ((P5) of FIG. 14) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the third node, having a second electrode connected the fourth node and having a substrate connected said fourth node, is newly introduced.
The third modification (This corresponds to claim 24.) is the input circuit defined in claim 16 to which:
an input terminal connected the third node,
an output terminal connected the fifth node,
a seventeenth normally off type field effect transistor ((N1) of FIG. 14) having a channel of the opposite conductivity, having a gate connected the second power supply, having a first electrode connected the second power supply and having a second electrode connected the eighth node, and
an eighteenth normally off type field effect transistor ((N2) of FIG. 14) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the eighth node and having a second electrode connected the third node
are newly introduced.
An input circuit (This corresponds to claim 25.) in accordance with the tenth embodiment of this invention described referring to FIG. 20 is the input circuit defined in claim 24 to which a nineteenth normally off type field effect transistor ((N23) of FIG. 20) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the eighth node and having a second electrode connected the second power supply, is newly introduced.
An input circuit (This corresponds to claim 26.) in accordance with the eleventh embodiment of this invention described referring to FIG. 21 is defined as:
an input circuit comprising:
an input terminal connected a first node,
a first normally off type field effect transistor ((P31) of FIG. 21) having a channel of one conductivity, having a gate connected the first node, having a first electrode connected a first power supply, having a second electrode connected a second node which is floating and having a substrate connected a second node which is floating,
a second normally off type field effect transistor ((P32) of FIG. 21) having a channel of one conductivity, having a gate connected the first power supply having a first electrode connected the first node, having a second electrode connected a third node and having a substrate connected the second node,
a load circuit means having a first terminal connected the third node and a second terminal connected the second power supply,
a third normally off type field effect transistor ((N37) of FIG. 21) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the third node and having a second electrode connected a fourth node,
a comparator circuit means having an input terminal connected the fourth node and having an output terminal connected a fifth node, and
an output terminal connected the fifth node.
An input circuit (This corresponds to claim 27.) in accordance with the twelfth embodiment of this invention described referring to FIG. 24 is defined as:
an input circuit comprising:
an input terminal connected a first node,
a first normally off type field effect transistor ((P31) of FIG. 24) having a channel of one conductivity, having a gate connected the first node, having a first electrode connected a first power supply, having a second electrode which is floating and having a substrate connected a second node which is floating,
a second normally off type field effect transistor ((P32) of FIG. 24) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the first node, having a second electrode connected a third node and having a substrate connected the second node,
a load circuit means having a first terminal connected the third node and having a second terminal connected a second power supply,
a third normally off type field effect transistor ((N37) of FIG. 24) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the third node and having a second electrode connected a fourth node,
a fourth normally off type field effect transistor ((N38) of FIG. 24) having a channel of the opposite conductivity, having a gate connected the fourth node, having a first electrode connected a fifth node and having a second electrode connected the second power supply,
a fifth normally off type field effect transistor ((P38) of FIG. 24) having a channel of one conductivity, having a gate connected the fourth node, having a first electrode connected a sixth node, having a second electrode connected the fifth node and having a substrate connected the sixth node,
an inverter means having an input terminal connected the fifth node and having an output terminal connected a seventh node,
a sixth normally off type field effect transistor ((P39) of FIG. 24) having a channel of one conductivity, having a gate connected the seventh node, having a first electrode connected the first power supply and having a second electrode connected the sixth node,
a seventh normally off type field effect transistor ((N39) of FIG. 24) having a channel of the opposite conductivity, having a gate connected the seventh node, having a first electrode connected the sixth node and having a second electrode connected the first power supply, and
an output terminal connected the seventh node.
An input/output circuit (This corresponds to claim 28.) can be produced by combining an output circuit defined by claim 15 and an input circuit defined by claim 26, and by connecting the third input terminal of the output circuit and the second output terminal of the input circuit, the first output terminal of the output circuit and an external circuit, and the fifth input terminal of the input circuit and the power supply of the external circuit.
An input/output circuit (This corresponds to claim 29.) can be produced by combining an output circuit defined by claim 15 and an input circuit defined by claim 27, and by connecting the third input terminal of the output circuit and the second output terminal of the input circuit, the first output terminal of the output circuit and an external circuit, and the fifth input terminal of the input circuit and the power supply of the external circuit.
An input/output circuit (This corresponds to claim 30.) in accordance with the thirteenth embodiment of this invention described referring to FIG. 26 is defined as:
an input/output circuit comprising:
a first normally off type field effect transistor ((P1) of FIG. 26) having a channel of one conductivity, having a gate connected a first node, having a first electrode connected a first power supply and a second electrode connected a second node,
a second normally off type field effect transistor ((P2) of FIG. 26) having a channel of one conductivity, having a gate connected a third node, having a first electrode connected a second node, having a second electrode connected a fourth node and having a substrate connected a fifth node which is floating,
a third normally off type field effect transistor ((P4) of FIG. 26) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the third node, having a second electrode connected the fourth node and having a substrate connected the fifth node,
a fourth normally off type field effect transistor ((N7) of FIG. 26) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the fourth node and having a second electrode connected a sixth node,
a fifth normally off type field effect transistor ((P7) of FIG. 26) having a channel of one conductivity, having a gate connected the third node, having a first electrode connected the sixth node, having a second electrode connected the fourth node and having a substrate connected the fifth node,
an inverter means having an input terminal connected the sixth node and having an output terminal connected a seventh node,
a sixth normally off type field effect transistor ((N3) of FIG. 26) having a channel of the opposite conductivity, having a gate connected the seventh node, having a first electrode connected a second power supply and a second electrode connected an eighth node,
a seventh normally off type field effect transistor ((N4) of FIG. 26) having a channel of the opposite conductivity, having a gate connected a ninth node, having a first electrode connected a eighth node and having a second electrode connected a tenth node,
an eighth normally off type field effect transistor ((N5) of FIG. 26) having a channel of the opposite conductivity, having a gate connected an eleventh node, having a first electrode connected the tenth node and having a second electrode connected the first node, and
a ninth normally off type field effect transistor ((N9) of FIG. 26) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the tenth node and having a second electrode connected the third node.
Four modifications stem from the foregoing input/output circuit defined in claim 30.
The first modification (This corresponds to claim 31.) is the input/output circuit defined in claim 30 to which a tenth normally off type field effect transistor ((P6) of FIG. 26) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the first power supply and having a second electrode connected the sixth node, is newly introduced.
The second modification (This corresponds to claim 32.) is the input/output circuit defined in claim 30 to which an eleventh normally off type field effect transistor ((P3) of FIG. 26) having a channel of one conductivity, having a gate connected the third node, having a first electrode connected the second node, having a second electrode connected the fifth node, and having a substrate connected the fifth node, is newly introduced.
The third modification (This corresponds to claim 33.) is the input/output circuit defined in claim 30 to which a twelfth normally off type field effect transistor ((P5) of FIG. 26) having a channel of one conductivity, having a gate connected the first power supply, having a first electrode connected the fourth node, having a second electrode connected the fifth node and having a substrate connected the fifth node, is newly introduced.
The fourth modification (This corresponds to claim 34.) is the input/output circuit defined in claim 30 to which:
a first input terminal connected the first node,
a second input terminal connected the eleventh node,
a third input terminal connected the ninth node,
a fourth input terminal connected an eleventh node,
an output terminal connected the sixth node,
an input/output terminal connected the fourth node,
a thirteenth normally off type field effect transistor ((N1) of FIG. 26) having a channel of the opposite conductivity, having a gate connected the twelfth node, having a first electrode connected the second power supply and a second electrode connected a thirteenth node, and
a fourteenth normally off type field effect transistor ((N2) of FIG. 26) having a channel of the opposite conductivity, having a gate connected the first power supply, having a first electrode connected the thirteenth node and having a second electrode connected the fourth node
are newly introduced.